Filter, Snubber, Dead Time: Where the Real EMC Decisions Are Made in Hybrid Inverters

A 15 kW hybrid inverter in the field has to serve two worlds simultaneously: the grid connection with its requirements for harmonics, Q(U) control and fault behavior, and the DC side with PV strings whose ground capacitance dominates the EMC budget. Anyone treating both sides as separate problems misses precisely the couplings that become expensive later in the test lab.

What follows are six design levers that, in practice, make the difference between “barely passed” and “certified with margin”.

1. LCL Instead of LC Filter: Not a Matter of Taste, But a System Decision

An LC filter is sufficient for island operation or applications with a defined load impedance. The moment the inverter couples to the public grid, grid impedance becomes the unknown variable. It varies with time of day, local network topology and the switching state of neighboring generators. This is exactly where the second inductor of an LCL filter pays back its cost. It decouples the internal filter behavior from the grid and makes the switching ripple injection into the grid manageable.

In numbers: for a typical 15 kW design at 16 kHz switching frequency, a well-dimensioned LCL filter can achieve damping of ripple currents at switching frequency in the range of 60 to 80 dB. A comparable LC filter stays stuck at 30 to 40 dB. That difference determines whether the common-mode choke ahead of it ends up small or large, and with it the bill of materials, losses and material cost.

2. Resonance Damping: Active Beats Passive, But Not Without Conditions

The transfer function of an LCL filter is third order with a pronounced resonance peak. The undamped pole sits at

f_res = (1 / 2π) · √((L1 + L2) / (L1 · L2 · C_f))

Without damping, the closed loop is unstable. Classically, a damping resistor is added in series with the filter capacitor. That works, but costs 1 to 3 percent in efficiency and creates thermal hotspots at the filter.

Active damping via capacitor current feedback is the more elegant solution. An additional current measurement at the filter capacitor is fed back into the inner current controller through a virtual resistor value. Advantages: no losses, freely tunable damping, no hardware change. Disadvantage: the method requires the resonance frequency to lie within the controller bandwidth, and the sampling frequency must be high enough, typically at least ten times the resonance frequency.

Practical issue: with weak grids the effective resonance frequency shifts, because the grid inductance acts in series with L2. The controller must tolerate this shift. Robust designs verify stability over an SCR (short circuit ratio) range of 2 to 20.

3. THDi Under Partial Load: The Real Stress Test

VDE-AR-N 4105 demands harmonic compliance not only at rated power but across the entire operating range. Most inverters pass the test at 100 percent comfortably and fail at 10 or 20 percent load. The reason is physical: the fundamental scales linearly with power, but the distortion components from dead time, switch voltage drops and DC-link ripple do not.

Representative bench result for a non-optimized design: at 100 percent THDi 1.8 percent, at 25 percent THDi 4.5 percent, at 10 percent THDi 8 percent or worse. The 5th and 7th harmonics dominate, both primarily dead-time induced.

The countermeasures, in order of effectiveness:

  1. Dead-time compensation based on measured current direction

  2. Adaptive bias to avoid zero-crossing distortion

  3. Resonant current controllers with additional resonant terms at 5f and 7f

  4. High-resolution current measurement with low quantization noise

A design that implements all four keeps THDi below 5 percent even at 10 percent load. That is the real quality benchmark of an inverter, not the value at rated power.

4. Common-Mode Currents and Y-Capacitor Sizing: The Regulatory Bottleneck

In three-phase two-level inverters, the common-mode voltage u_cm = (u_A + u_B + u_C) / 3 alternates between levels of ±U_DC/2 (at the zero vectors) and ±U_DC/6 (at the active vectors). Each switching transition between an active vector and a zero vector produces a step of U_DC/3. These voltage steps drive currents through the ground capacitance of the PV generator and through the Y-capacitors of the EMC filter into the protective earth conductor.

The regulatory limits are unambiguous. IEC 62109-2 specifies, for transformerless inverters, the response thresholds of an all-current sensitive residual current monitoring unit (RCMU) that detects AC and DC components together. A sudden residual current change of 30 mA must lead to disconnection within 300 ms; 60 mA within 150 ms; 150 mA within 40 ms. The continuous residual current must not exceed 300 mA in total for units up to 30 kVA, scaling at 10 mA per kVA of rated power for larger units.

DIN V VDE V 0126-1-1:2013-08 still formally exists as a preliminary standard, but its original requirements on functional safety and residual current monitoring have been transferred to DIN EN 62109-2, and those on islanding detection to VDE-AR-N 4105 (current edition 2026-03). The protection concept and the threshold values have been preserved.

Hence the Y-capacitor dilemma: for good EMC damping you want large Y-capacitors, for low leakage current you want small ones. In practice, transformerless 15 kW hybrid inverters operate in a range from a few nF up to roughly 47 nF per phase, depending on the expected ground capacitance of the PV generator and the common-mode loading of the chosen topology and modulation strategy. Beyond the steady-state leakage current, the design must also handle the transient CM current pulses produced by every switching edge, which can trigger the RCMU.

Structural levers beyond the Y-capacitors:

  • Common-mode choke directly at the inverter output, not only after the LCL filter

  • Symmetric DC wiring to reduce the effective common-mode driving signal

  • Modulation strategies such as AZSPWM or RSPWM that reduce the count and amplitude of common-mode steps, at the cost of higher differential-mode distortion or a restricted modulation index

  • At higher power levels: switch to three-level NPC or T-Type topology, which structurally produces smaller CM voltage steps (max. ±U_DC/3 instead of ±U_DC/2)

5. Snubbers in the SiC Era: Less Energy, More Bandwidth

Classic RC and RCD snubbers were designed for IGBTs switching at dv/dt in the range of 5 to 10 kV/µs. SiC MOSFETs reach 30 to 50 kV/µs, and that changes the rules of the game.

First, parasitic loop inductances between DC-link capacitor and switch should stay below roughly 10 nH, otherwise overshoot dominates the snubber. PCB layout beats snubbers every day. DC-link ceramic capacitors as close as possible to the drain, separate current loops for power and control circuit.

Second, the focus shifts from drain-source snubbers to gate-side measures: separate gate resistors for turn-on and turn-off, ferrite beads to damp the gate loop where appropriate, active Miller clamping. This makes the EMC behavior controllable without massively increasing switching losses.

Third, a small RC snubber directly at the DC-bus terminals of the half-bridge module can damp the high-frequency content above 30 MHz that would otherwise show up in the conducted EMC spectrum. Typical values around 2.2 Ω and 1 nF, dissipation below 1 W. That is investment in EMC pre-test margin, not in efficiency loss.

6. Dead Time: The Underestimated Variable

Dead time prevents shoot-through caused by simultaneously conducting half-bridge switches. Too little dead time means short circuit, too much means voltage distortion that appears as harmonics in the current and directly aggravates the partial-load issue described in section 3.

IGBTs historically required 1 to 3 µs dead time. SiC MOSFETs operate with 50 to 200 ns, provided the gate design plays along. This single factor reduces dead-time induced distortion by an order of magnitude.

For the last few percent, adaptive dead time based on measured current direction pays off: at small currents the driver logic conservatively extends dead time, at high currents it shortens to the minimum that is still thermally and electrically safe. Combined with software-side dead-time compensation that pre-corrects the voltage error directly in the modulator, THDi values below 1.5 percent at rated power are achievable.

7. What This Means for System Design

The six levers do not act independently. A decision for SiC enables higher switching frequencies, which in turn allow smaller LCL components and shorter dead times, improving THDi under partial load. At the same time dv/dt rises, aggravating common-mode issues and putting pressure on the Y-capacitor choice. Active filter damping permits leaner filters but depends on controller bandwidth, which is itself limited by switching frequency.

Anyone addressing EMC only at the end of the development process turns individual screws and merely shifts the problem. Anyone treating topology, modulation, filter, gate driver and control as a coupled system achieves compliance with margin, and an efficiency that is not bought at the expense of grid quality.

In the ampareq Gen3 program at awb-it we draw exactly this line: every design decision in the power path is checked against the EMC budget before it is released. The test lab then becomes verification, not diagnosis.

If you encounter similar conflicts between efficiency, grid quality and EMC in your own development work, I would be glad to exchange experiences in the comments or via direct message.

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